From: Mark Date: Sun, 29 Oct 2023 00:13:42 +0000 (-0600) Subject: fix signed modulus bug (#2134) X-Git-Tag: remove~3 X-Git-Url: https://git.sagredo.dev/?a=commitdiff_plain;h=ae7cf15c7044fc3295aef9ad9d17433169691955;p=scryer-prolog.git fix signed modulus bug (#2134) --- diff --git a/src/machine/arithmetic_ops.rs b/src/machine/arithmetic_ops.rs index 92e9c599..20c503a9 100644 --- a/src/machine/arithmetic_ops.rs +++ b/src/machine/arithmetic_ops.rs @@ -1,4 +1,4 @@ -use dashu::base::{Abs, Gcd, UnsignedAbs}; +use dashu::base::{Abs, Gcd, Signed, UnsignedAbs}; use dashu::integer::IBig; use dashu::integer::fast_div::ConstDivisor; use divrem::*; @@ -852,7 +852,18 @@ pub(crate) fn modulus(x: Number, y: Number, arena: &mut Arena) -> Result Integer { let ring = ConstDivisor::new(n2.unsigned_abs()); let n1 = n1.clone(); - IBig::from(ring.reduce(n1).residue()) + + if n2.is_negative() { + let unsigned_result = IBig::from(ring.reduce(n1).residue()); + + if unsigned_result.is_zero() { + unsigned_result + } else { + unsigned_result + n2 + } + } else { + IBig::from(ring.reduce(n1).residue()) + } } match (x, y) {