From: Mark Thom <markjordanthom@gmail.com>
Date: Mon, 18 Mar 2019 03:45:30 +0000 (-0600)
Subject: correct register threshold calculation.
X-Git-Tag: v0.8.110~165
X-Git-Url: https://git.sagredo.dev/?a=commitdiff_plain;h=55a251d1c478120c4759815805a34760f27c5ced;p=scryer-prolog.git

correct register threshold calculation.
---

diff --git a/src/prolog/machine/attributed_variables.rs b/src/prolog/machine/attributed_variables.rs
index 174f89f4..9301fdff 100644
--- a/src/prolog/machine/attributed_variables.rs
+++ b/src/prolog/machine/attributed_variables.rs
@@ -59,17 +59,10 @@ impl MachineState {
 
     pub(super)
     fn calculate_register_threshold(&self) -> usize {
-        let mut count = 0;
-
-        for r in 1 .. MAX_ARITY + 1 {
-            if let &Addr::HeapCell(0) = &self[RegType::Temp(r)] {
-                break;
-            }
-
-            count += 1;
-        }
-
-        count
+        /* for all we know, all registers might be valid when we
+         * return from the verify_attributes interrupt. we currently
+         * lack a more precise way of determining this. */
+        MAX_ARITY
     }
 
     fn verify_attributes(&mut self)
diff --git a/src/prolog/machine/compile.rs b/src/prolog/machine/compile.rs
index b2bb3914..ec615a46 100644
--- a/src/prolog/machine/compile.rs
+++ b/src/prolog/machine/compile.rs
@@ -341,13 +341,13 @@ fn add_module_code(wam: &mut Machine, mut module: Module, code: Code, mut indice
 
     module.code_dir.extend(code_dir);
     module.op_dir.extend(op_dir.into_iter());
-    
+
     for (name, arity) in indices.code_dir.keys().cloned() {
         if name.owning_module() == module.module_decl.name {
             wam.indices.dynamic_code_dir.remove(&(name.owning_module(), name, arity));
         }
-    }    
-    
+    }
+
     wam.add_module(module, code);
 }