From: Mark <markjordanthom@gmail.com>
Date: Sun, 8 Oct 2023 00:48:49 +0000 (-0600)
Subject: mark both components of a PStrLoc (#2082)
X-Git-Tag: remove~46
X-Git-Url: https://git.sagredo.dev/?a=commitdiff_plain;h=1ab14ea5193597f6c43e25623bfb203acdc0bd6b;p=scryer-prolog.git

mark both components of a PStrLoc (#2082)
---

diff --git a/src/heap_iter.rs b/src/heap_iter.rs
index e144ae3e..ef5e4ac5 100644
--- a/src/heap_iter.rs
+++ b/src/heap_iter.rs
@@ -80,9 +80,9 @@ impl<'a> EagerStackfulPreOrderHeapIter<'a> {
                 }
                 (HeapCellValueTag::AttrVar | HeapCellValueTag::Var, h) => {
                     let var_value = self.heap[h];
+                    self.heap[h].set_mark_bit(self.mark_phase);
 
                     if !(var_value.is_var() && var_value.get_value() as usize == h) {
-                        self.heap[h].set_mark_bit(self.mark_phase);
                         self.iter_stack.push(var_value);
                         continue;
                     }
@@ -99,8 +99,12 @@ impl<'a> EagerStackfulPreOrderHeapIter<'a> {
                         continue;
                     }
 
+                    let value = self.heap[h+1];
+
                     self.heap[h].set_mark_bit(self.mark_phase);
-                    self.iter_stack.push(self.heap[h+1]);
+                    self.heap[h+1].set_mark_bit(self.mark_phase);
+
+                    self.iter_stack.push(value);
                 }
                 _ => {
                 }