From: Mark Thom <markjordanthom@gmail.com>
Date: Fri, 7 Jan 2022 05:18:46 +0000 (-0700)
Subject: update README.md
X-Git-Tag: v0.9.0^2~91
X-Git-Url: https://git.sagredo.dev/?a=commitdiff_plain;h=06313cac64d1379f75b103e46d00bf682283034f;p=scryer-prolog.git

update README.md
---

diff --git a/README.md b/README.md
index 09878933..2db7b76e 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,25 @@ programming, which is itself written in a high-level language.
 
 ![Scryer Logo: Cryer](logo/scryer.png)
 
+# Rebis Development Branch
+
+![Art Card](logo/art_card.jpg)
+
+This is the Rebis Development Branch (rebis-dev). This iteration of
+Rebis contains sweeping changes to the instruction dispatch loop
+alongside a compacted heap representation. These changes are to
+enhance the performance and robustness of Scryer Prolog and to prepare
+for the introduction of a mark-compacting garbage collector.
+
+Several performance enhancing changes are due before rebis-dev will be
+considered ready for merging into master, among them:
+
+* Replacing choice points pivoting on inlined deterministic predicates
+  (`atom`, `var`, etc) with if/else ladders
+* Inlining all built-ins and system call instructions
+* Greatly reducing the number of instructions used to compile disjunctives
+* Storing short atoms to heap cells without writing them to the atom table
+
 ## Phase 1
 
 Produce an implementation of the Warren Abstract Machine in Rust, done
diff --git a/logo/art_card.jpg b/logo/art_card.jpg
new file mode 100644
index 00000000..27b21ba3
Binary files /dev/null and b/logo/art_card.jpg differ
diff --git a/src/machine/machine_state.rs b/src/machine/machine_state.rs
index 6da9674b..11b2672a 100644
--- a/src/machine/machine_state.rs
+++ b/src/machine/machine_state.rs
@@ -499,13 +499,6 @@ impl MachineState {
                     }
 
                     let mut singleton_var_set: IndexMap<Ref, bool> = IndexMap::new();
-                    let mut var_list = vec![];
-
-                    let list_of_var_eqs = push_var_eq_functors(
-                        &mut self.heap,
-                        term_write_result.var_dict.iter(),
-                        &mut self.atom_tbl,
-                    );
 
                     for addr in stackful_preorder_iter(&mut self.heap, term) {
                         let addr = unmark_cell_bits!(addr);
@@ -513,7 +506,6 @@ impl MachineState {
                         if let Some(var) = addr.as_var() {
                             if !singleton_var_set.contains_key(&var) {
                                 singleton_var_set.insert(var, true);
-                                var_list.push(addr);
                             } else {
                                 singleton_var_set.insert(var, false);
                             }
@@ -532,6 +524,23 @@ impl MachineState {
                         &mut self.atom_tbl,
                     );
 
+                    let mut var_list = Vec::with_capacity(singleton_var_set.len());
+
+                    for (var_name, addr) in term_write_result.var_dict {
+                        if let Some(var) = addr.as_var() {
+                            let idx = singleton_var_set.get_index_of(&var).unwrap();
+                            var_list.push((var_name, addr, idx));
+                        }
+                    }
+
+                    var_list.sort_by(|(_,_,idx_1),(_,_,idx_2)| idx_1.cmp(idx_2));
+
+                    let list_of_var_eqs = push_var_eq_functors(
+                        &mut self.heap,
+                        var_list.iter().map(|(var_name, var,_)| (var_name,var)),
+                        &mut self.atom_tbl,
+                    );
+
                     let singleton_addr = self.registers[3];
                     let singletons_offset = heap_loc_as_cell!(
                         iter_to_heap_list(&mut self.heap, singleton_var_list.into_iter())
@@ -545,7 +554,7 @@ impl MachineState {
 
                     let vars_addr = self.registers[4];
                     let vars_offset = heap_loc_as_cell!(
-                        iter_to_heap_list(&mut self.heap, var_list.into_iter())
+                        iter_to_heap_list(&mut self.heap, var_list.into_iter().map(|(_,cell,_)| cell))
                     );
 
                     unify_fn!(*self, vars_offset, vars_addr);