unmark cell bits in occurs check

diff --git a/src/machine/machine_state_impl.rs b/src/machine/machine_state_impl.rs
index 1caa8a96ad730fe4ddb88ba56b05952d1b987877..47019772f9b0f113541bde4a0149f5b9aed91cb9 100644 (file)
--- a/src/machine/machine_state_impl.rs
+++ b/src/machine/machine_state_impl.rs
@@ -882,6 +882,8 @@ impl MachineState {
 
         if !value.is_constant() {
             for addr in stackful_preorder_iter(&mut self.heap, value) {
+                let addr = unmark_cell_bits!(addr);
+
                 if let Some(inner_r) = addr.as_var() {
                     if r == inner_r {
                         occurs_triggered = true;