generate module-level expansion code along with rest of module code

diff --git a/src/prolog/machine/compile.rs b/src/prolog/machine/compile.rs
index 19a20425f613d957beefb50717828c207310989d..b24584df3590155377848c2dfa039e4c5e78aaa8 100644 (file)
--- a/src/prolog/machine/compile.rs
+++ b/src/prolog/machine/compile.rs
@@ -920,7 +920,17 @@ fn compile_work_impl(
     mut indices: IndexStore,
     mut results: GatherResult,
 ) -> Result<(), SessionError> {
-    let mut module_code = compiler.generate_code(
+    if let Some(ref mut module) = &mut compiler.module {
+        // compile the module-level goal and term expansions and store
+        // their locations to the module's code_dir.
+        let decls = module.take_local_expansions();
+            
+        if !decls.is_empty() {
+            results.worker_results.extend(decls.into_iter());
+        }
+    }
+    
+    let module_code = compiler.generate_code(
         results.worker_results,
         wam,
         &mut indices.code_dir,
@@ -972,16 +982,6 @@ fn compile_work_impl(
             wam.indices.use_module(&mut wam.code_repo, wam.machine_st.flags, &module)?;
             wam.indices.insert_module(module);
         } else {                  
-            // compile the module-level goal and term expansions and store
-            // their locations to the module's code_dir.
-            let offset = module_code.len() + toplvl_code.len();
-            let decls = module.take_local_expansions();
-            
-            if !decls.is_empty() {
-                let code = compiler.generate_code(decls, &wam, &mut indices.code_dir, offset)?;
-                module_code.extend(code.into_iter());
-            }
-
             add_module_code(wam, module, module_code, indices);
         }
 

diff --git a/src/prolog/machine/machine_state_impl.rs b/src/prolog/machine/machine_state_impl.rs
index 7392d65c234246a1f6884a99edab990000308a7a..60713510d34ab465c15c8d104022965b08f3dc19 100644 (file)
--- a/src/prolog/machine/machine_state_impl.rs
+++ b/src/prolog/machine/machine_state_impl.rs
@@ -3080,14 +3080,15 @@ impl MachineState {
                 | (
                     HeapCellValue::Addr(v1 @ Addr::StackCell(..)),
                     HeapCellValue::Addr(v2 @ Addr::HeapCell(_)),
-                ) => match (var_pairs.get(&v1).cloned(), var_pairs.get(&v2).cloned()) {
-                    (Some(ref v2_p), Some(ref v1_p)) if *v1_p == v1 && *v2_p == v2 => continue,
-                    (Some(_), _) | (_, Some(_)) => return true,
-                    (None, None) => {
-                        var_pairs.insert(v1.clone(), v2.clone());
-                        var_pairs.insert(v2, v1);
-                    }
-                },
+                ) =>
+                    match (var_pairs.get(&v1).cloned(), var_pairs.get(&v2).cloned()) {
+                        (Some(ref v2_p), Some(ref v1_p)) if *v1_p == v1 && *v2_p == v2 => continue,
+                        (Some(_), _) | (_, Some(_)) => return true,
+                        (None, None) => {
+                            var_pairs.insert(v1.clone(), v2.clone());
+                            var_pairs.insert(v2, v1);
+                        }
+                    },
                 (HeapCellValue::Addr(a1), HeapCellValue::Addr(a2)) => {
                     if a1 != a2 {
                         return true;