]> Repositorios git - scryer-prolog.git/commitdiff
consider Str, PStrLoc in ElideLists of StackfulHeapIterator (#2075)
authorMark <[email protected]>
Wed, 4 Oct 2023 06:26:44 +0000 (00:26 -0600)
committerMark <[email protected]>
Wed, 4 Oct 2023 06:27:01 +0000 (00:27 -0600)
src/heap_iter.rs

index ffb8df904210d23506ed06f25e9f7637d69e546e..0bfbd46552a65f6a6e31f8bf533252c3248725b7 100644 (file)
@@ -236,17 +236,17 @@ impl<'a, ElideLists: ListElisionPolicy> StackfulPreOrderHeapIter<'a, ElideLists>
         let cell = self.read_cell(loc);
 
         read_heap_cell!(cell,
-            (HeapCellValueTag::Lis, vh) => {
+            (HeapCellValueTag::Lis |
+             HeapCellValueTag::Str |
+             HeapCellValueTag::PStrLoc, vh) => {
                 let forward = if ElideLists::elide_lists() { true } else { cell.get_mark_bit() };
 
                 if forward && self.heap[vh].get_mark_bit() {
                     self.read_cell_mut(loc).set_forwarding_bit(true);
                 }
             }
-            (HeapCellValueTag::Str |
-             HeapCellValueTag::AttrVar |
-             HeapCellValueTag::Var |
-             HeapCellValueTag::PStrLoc, vh) => {
+            (HeapCellValueTag::AttrVar |
+             HeapCellValueTag::Var, vh) => {
                 if self.heap[vh].get_mark_bit() {
                     self.read_cell_mut(loc).set_forwarding_bit(true);
                 }