]> Repositorios git - scryer-prolog.git/commitdiff
mark both components of a PStrLoc (#2082)
authorMark <[email protected]>
Sun, 8 Oct 2023 00:48:49 +0000 (18:48 -0600)
committerMark <[email protected]>
Sun, 8 Oct 2023 00:48:49 +0000 (18:48 -0600)
src/heap_iter.rs

index e144ae3e10df44aa016a8d37a2b0e1370ddb00e8..ef5e4ac5bab29c62022e6aa0c0a73d1b84db3eaf 100644 (file)
@@ -80,9 +80,9 @@ impl<'a> EagerStackfulPreOrderHeapIter<'a> {
                 }
                 (HeapCellValueTag::AttrVar | HeapCellValueTag::Var, h) => {
                     let var_value = self.heap[h];
+                    self.heap[h].set_mark_bit(self.mark_phase);
 
                     if !(var_value.is_var() && var_value.get_value() as usize == h) {
-                        self.heap[h].set_mark_bit(self.mark_phase);
                         self.iter_stack.push(var_value);
                         continue;
                     }
@@ -99,8 +99,12 @@ impl<'a> EagerStackfulPreOrderHeapIter<'a> {
                         continue;
                     }
 
+                    let value = self.heap[h+1];
+
                     self.heap[h].set_mark_bit(self.mark_phase);
-                    self.iter_stack.push(self.heap[h+1]);
+                    self.heap[h+1].set_mark_bit(self.mark_phase);
+
+                    self.iter_stack.push(value);
                 }
                 _ => {
                 }